This invention relates to a presettable swallow counter capable of operating at a high speed.
A prior art high speed counter has been constituted by a plurality of frequency division circuits each constituted by a TTL logic circuit or an ECL logic circuit utilizing bipolar transistors, but because of its large power consumption there was a limit for a large frequency division ratio that can be obtained by cascade connecting a large number of frequency division circuits. Moreover, the temperature rise during operation is large and the area occupied by the circuit is also large so that it has been impossible to manufacture a large single chip integrated circuit.
Consequently, a swallow counter as shown in FIG. 1 which is characterized by a high operating speed and a high variable frequency ratio has been used. The overall power consumption of the frequency division circuit is small because the counter comprises a first stage counter in the form of a high speed counter (for example, a counter constituted by bipolar transistors) and a succeeding stage counter in the form of a low speed counter (for example, a counter constituted by MOS transistors). In addition, such frequency division circuit enables one to fabricate a high density integrated circuit as well as a presettable counter capable of operating at a high speed.
FIG. 1 shows a prior art presettable swallow counter comprising an input terminal 1, a 2 modulus prescaler (2 coefficient prestage frequency division circuit)2, a first programable counter 3, a second programable counter 4, a first code detector 5, a second code detector 6, a prescaler control flip-flop circuit 7, a first preset data signal input terminal 9, a second preset data signal input terminal 10, an output terminal 11, and a prescaler control signal input terminal 12. The first and second programable counters 3 and 4, the first and second code detectors 5 and 6 and the prescaler control flip-flop circuit 7 constitute a programable divider block 8.
The operation of a prior art presettable swallow counter will be described hereunder with reference to FIG. 1 on the assumption that the first and the second programable counters 3 and 4 operate as programable down counters but not as up counters. In the latter case, since it is necessary to use complements as data, for the sake of brevity this case will not be described. Although the first and second code detectors 5 and 6 can detect any value, it is assumed now that they detect a count of zero.
A pulse inputted to the input terminal 1 is supplied to the 2 modulus prescaler 2. Where the frequency division ratio of the 2 modulus prescaler 2 is selected to be P+1 by the prescaler control flip-flop circuit 7, the 2 modulus prescaler 2 reduces the frequency of the input pulse to 1/P+1 and applies its reduced frequency output to the first programable counter 3 and the second programable counter 4.
The first and second programable counters 3 and 4 are set with data in accordance with the first and second preset data signals supplied from input terminals 9 and 10. In response to the output of the 2 modulus prescaler 2, the first and second programable counters 3 and 4 begin to count down from the set values described above. The outputs of the first and second programable counters 3 and 4 are supplied to the first and second code detectors 5 and 6, respectively.
Due to the construction of the swallow counter, it is necessary to set the maximum number that can be set in the first programable counter 3 to a value less than the maximum value that can be set in the second programable counter 4.
Representing any value that can be set in the first programable counter 3 by A, and any value that can be set in the second programable counter 4 by B, the count of the first programable counter 3 becomes zero when (P+1)A pulses are applied to the input terminal 1 and this zero count is detected by the first code detector 5 for resetting the prescaler control flip-flop circuit 7.
The output of the flip-flop circuit 7 when it is reset is supplied to the 2 modulus prescaler 2 via a control signal line 12. Depending upon the level of this control signal, the ratio of frequency division of the 2 modulus prescaler 2 is switched from 1/(p+1) to 1/P.
At this time, the count of the second programable counter 4 becomes equal to B-A. Consequently, when P.times.(B-A) pulses are applied thereafter to the input terminal 1, the count of the second programable counter 4 becomes zero so that the second code detector 6 operates to produce a single pulse at the output terminal 1.
The output pulse of the second code detector 6 sets the prescaler control flip-flop circuit 7 to cause it to transmit a set signal to the 2 modulus prescaler 2 for changing its ratio of frequency division to 1/(p+1) from 1/P.
Furthermore, the output pulse of the second code detector 6 is inputted to the first and second programable counters 3 and 4 so that these counters 3 and 4 are preset again with values A and B respectively represented by the first and second preset data signals at the input terminals 9 and 10 respectively, whereby one period is completed so as to begin the next counting.
As can be noted from the foregoing description, the total number N of frequency division of one period of the presettable swallow counter shown in FIG. 1 is expressed by the following equation. ##EQU1##
As one example of the presettable swallow counter, a presettable swallow counter utilizing a decimal counter as one unit will be described hereunder together with the defects of the prior art system.
Where a binary counter is used as a unit, in the equation just described P=10 and P+1=11. Thus, the equation becomes EQU N=10B+A
where A is an integer of from 0 to 9 and B is an integer larger than 10.
Waveform C shown in FIG. 2 shows the input to the input terminal 1 shown in FIG. 1; waveform F shows the output pulse of the 2 modulus prescaler 2 when it is supplied with the waveform C, and waveform D shows the output signal or pulse of the prescaler control flip-flop circuit 7. Furthermore, waveform E shows the output pulse appearing at the output terminal 11 shown in FIG. 1. It should be understood that these waveforms correspond to those when 2 of the digital BCD code is set in the first programable counter 3.
Although intermediate portions of the waveforms are omitted in FIG. 2, there are (10.times.B+A) input pulses of the waveform C between a building up and the next building down of the waveform E.
In order to establish a counter equation N=PB+A of the swallow type, the frequency is reduced to 1/11 with the 2 modulus prescaler when the prescaler control pulse shown by waveform D is at an H level, and to 1/10 when the prescaler control pulse is at an L level. The delay of the waveform D (prescaler control pulse) with respect to the waveform F (2 modulus prescaler output pulse) presents a problem.
In the waveform D shown in FIG. 2, a case wherein the delay thereof with reference to waveform F is shown by solid lines. The maximum limit necessary to hold the counter equation N=PB+A of the swallow system is shown by dotted lines and the areas between solid (delay zero) and dotted lines are shown as being cross-hatched. In FIG. 2, a delay range at the time of building up of the waveform D is shown by T.sub.1, and the range at the time of building down of the waveform D is shown by T.sub.2.
Where the presettable swallow counter is used for decreasing the frequency in a radio frequency band, the input frequency would be 130 MHz at the maximum (actually it is 120 MHz, the difference 10 MHz is a margin). For this reason, times T.sub.1 and T.sub.2 are expressed as follows: ##EQU2## This means that it is necessary to limit the delay of the prescaler control pulse with reference to the prescaler output pulse to be shorter than these times. If the delay of the prescaler control pulse with reference to the prescaler output pulse becomes larger than these times, either one of the interval 1/11 or 1/10 becomes longer thus resulting in an abnormal frequency division which causes a count error.
Where the 2 modulus prescaler 2 shown in FIG. 1 is constituted by an ECL while the other programable divider block 8 is constituted by a C-MOS, the frequency division of the input frequency 130 MHz can efficiently be realized with the ECL. However, with C-MOS, in view of the varieties in the source voltage and the ambient temperature, the delay of the prescaler control pulse with reference to the prescaler output pulse should be 250 ns at the minimum so that switching of the frequency division in such short delay time of less than T.sub.1 =77 ns and T.sub.2 =85 ns is practically impossible.
Accordingly, according to the prior art system, due to the delay time of the low speed counter in the later stage, the potential performance of the prescaler cannot be manifested sufficiently, thus limiting the overall characteristics of the swallow counter.